Cockpit Mission Display Processor

The Cockpit Mission Display Processor (CMDP) is a high safety avionics computer platform with a powerful embedded graphics capability. It is configured using the base of the standard hardware and layered software modules, both developed by adopting the latest quality standards that make the CMDP certifiable according to DO178B and DO254 level B (optionally level A) and suitable as a main cockpit mission computer.

The CMDP is capable of performing highly integrated mission management tasks including embedded dual head cockpit graphics generation and advanced digital map. It offers enhanced functionality, innovative graphical features, and an innovative Human Machine Interface (HMI).

It can be configured to the specific customer’s mission requirements utilizing a dedicated ground based software tool that is used for the main operating functions.

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  • Key Features
  • Technical Specifications
  • Management of the Tactical Situation Display, filtering of graphic data, layering of data
  • Management of platforms and missions using visualization of the interactive table of data, menu, and dialog windows
  • Management of the mission sensors including the settings for operating modes and working parameters
  • Integration of tactical data links to allow execution of cooperating missions

The CMDP uses an embedded mass memory to store pre-flight data such as map databases, intelligence data, and navigation data and to store data history for flight, mission, and maintenance purposes. A typical system configuration for a cockpit mission system includes a single (or optionally dual) CMDP, one or more displays, and external sensors from which A/C data and tactical information can be acquired to accomplish the mission.

MDP Physical Characteristics

  • Dimensions: 5 MCU
  • Weight: 9.5 Kg maximum
  • Power Requirements: 28 VDC
  • Power Dissipation: 85 W
  • Cooling: Convention cooled, closed enclosure
  • MTBF: 2500 operative hours
  • Connectors: Up to 9 connectors MIL- STD-38999 and 2 Triax for 1553 Avionic- Bus interfacing

Performances Processing & I/O

  • Performance:
    • (CPU Board) CPU Speed (frequency): 1.000 GHz
    • 2,000 DMIPS
    • 1 GB DDR SDRAM
  • Architecture: Modular Open System Architecture according to VITA 46 (VPX)
  • System Bus: System bus implemented using High speed Serial bus (PCIe)
  • Processor Architecture: Modular architecture based on the PCI and PCIe local buses
  • CPU: AMCC Processor PPC460EX @ 1 Ghz
  • I/O:
    • Interfaces Dual redundant MIL-STD-1553 Interface
    • RS4 22 serial interfaces
    • RS23 2 serial interfaces
    • Ethernet 10/100Base T
    • Arinc 429
    • USB
    • AFDX (optional)
    • Discrete and analogue
  • RT Operating System: GHS Integrity 178 B
  • Software Factory: ADA, C
  • OpenGL: Safety Critical OpenGL


  • Temperature: -40°C to +70°C (operating)
  • Vibration (random):
    • 0.0452 g2/Hz (lh/axis) Functional
    • 0.0125 g2/Hz (lh/axis) Endurance
  • EMC: In accordance with MIL-STD-810 and RTCA/DO-160

Applicable Standards

  • MIL-STD-810D
  • MIL-STD-704D
  • MIL-STD-462 (Test) & 461 (Req.)
  • MIL-STD-1553B
  • EIA-STD-RS422/485
  • STANAG S3350A, B, C , XGA (synch on green), DVI
  • RTCA DO-178B level B (optionally level A)
  • DO-254 level B
  • ARINC 429
  • VITA 42.0 & VITA 42.3

Options for Software

  • Equipment SW only, in accordance to DO-178B level B (optionally level A)
  • Equipment SW and Digital Map SW, in accordance to DO-178B level B (optionally level A)
  • Equipment SW and Operating Flight Program SW, including dual heads EFIS graphics generation, in accordance to DO-178B level B (optionally level A)

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